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1 copyright ? cirr u s logi c , i n c . 1997 (all rights reserv ed) cirrus log ic, inc. crys t al semi cond ucto r produc ts div i sio n p. o. box 178 47 , aus t in , te xa s 7 876 0 (5 12) 445 72 22 fax: (512 ) 44 5 7 581 h ttp : //www.c r y s ta l . c o m cs5101a cs5102a 16 -bit, 100 k h z / 2 0 khz a/d conv ert e rs features l monolithic cmos a/d converters - inherent sampling architecture - 2-channel input multiplexer - flexible serial output port l ultra-low distortion - s/(n+d): 92 db - thd: 0.001% l conversion time - cs5101a: 8 s - cs5102a: 40 s l linearity error: 0.001% fs - guaranteed no missing codes l self-calibration maintains accuracy - over time and temperature l low power consumption - cs5101a: 320 mw - cs5102a: 44 mw - power-down mode: <1 mw l evaluation board available description the cs5101a and cs5102a are 16-bit monolithic cmos analog-to-digital converters capable of 100 khz (5101a) and 20 khz (5102a) throughput. the cs5102a's low power consumption of 44 mw, coupled with a power down mode, makes it particularly suitable for battery powered operation. on-chip self-calibration circuitry achieves nonlinearity of 0.001% of fs and guarantees 16-bit no missing codes over the entire specified temperature range. superior lin- earity also leads to 92 db s/(n+d) with harmonics below -100 db. offset and full-scale errors are minimized dur- ing the calibration cycle, eliminating the need for external trimming. the cs5101a and cs5102a each consist of a 2-chan- nel input multiplexer, dac, conversion and calibration microcontroller, clock generator, comparator, and serial communications port. the inherent sampling architec- ture of the device eliminates the need for an external track and hold amplifier. the converters' 16-bit data is output in serial form with ei- ther binary or 2's complement coding. three output timing modes are available for easy interfacing to micro- controllers and shift registers. unipolar and bipolar input ranges are digitally selectable. ordering information s e e p a ge 3 6 . i clkin refbuf vref ain1 agnd hold sleep rst code bp/up trk1 trk2 ssh/sdl sdata sclk test dgnd vd- vd+ va- va+ 12 28 2 5 16 17 8 9 11 15 3 21 20 19 22 25 23 716 26 14 - + - + - + - + clock generator control calibration microcontroller comparator 16-bit charge sram redistribution dac stby crs/fin 10 xout 4 ain2 24 ch1/2 13 sckmod 27 outmod 18 mar 95 ds45f2
cs5101a-j,k cs5101a-a,b cs5101a-s,t parameter* min typ max min typ max min typ max units specified temperature range 0 to +70 -40 to +85 -55 to +125 c accuracy linearity error -j,a,s (note 1) -k,b,t drift (note 2) - - - 0.002 0.001 1/4 0.003 0.002 - - - - 0.002 0.001 1/4 0.003 0.002 - - - - 0.002 0.001 1/2 0.004 0.003 - %fs %fs d lsb differential linearity (notes 3, 4) 16 - - 16 - - 16 - - bits full scale error -j,a,s (note 1) -k,b,t drift (note 2) - - - 1 1 1 4 3 - - - - 1 1 1 4 3 - - - - 2 2 2 5 4 - lsb lsb d lsb unipolar offset -j,a,s (note 1) -k,b,t drift (note 2) - - - 2 2 1 5 4 - - - - 2 2 1 5 4 - - - - 2 2 2 5 4 - lsb lsb d lsb bipolar offset -j,a,s (note 1) -k,b,t drift (note 2) - - - 2 2 1 5 3 - - - - 2 2 2 5 3 - - - - 2 2 2 5 3 - lsb lsb d lsb bipolar negative full-scale error -j,a,s (note 1) -k,b,t drift (note 2) - - - 1 1 1 4 3 - - - - 1 1 1 4 3 - - - - 1 1 2 5 3 - lsb lsb d lsb dynamic performance (bipolar mode) peak harmonic or spurious noise (note 1) 1 khz input -j,a,s -k,b,t 12 khz input -j,a,s -k,b,t 96 98 85 85 100 102 88 91 - - - - 96 98 85 85 100 102 88 91 - - - - 94 98 83 85 100 102 88 91 - - - - db db db db total harmonic distortion -j,a,s -k,b,t - - 0.002 0.001 - - - - 0.002 0.001 - - - - 0.002 0.001 - - % % signal-to-noise ratio (note 1) 0db input -j,a,s -k,b,t -60 db input -j,a,s -k,b,t 87 90 - - 90 92 30 32 - - - - 87 90 - - 90 92 30 32 - - - - 87 90 - - 90 92 30 32 - - - - db db db db noise (note 5) unipolar mode bipolar mode - - 35 70 - - - - 35 70 - - - - 35 70 - - m v rms m v rms cs5101a analog characteristics (t a = t min to t max ; va+, vd+ = 5v; va-, vd- = -5v; vref = 4.5v; full-scale input sinewave, 1 khz; clkin = 4 mhz for -16, 8 mhz for -8; f s = 50 khz for -16, 100 khz for -8; bipolar mode; frn mode; ain1 and ain2 tied together, each channel tested separately; analog source impedance = 50 w with 1000 pf to agnd unless otherwise specified) notes: 1. applies after calibration at any temperature within the specified temperature range. at temp 2. total drift over specified temperature range after calibration at power-up at 25 c. 3. minimum resolution for which no missing codes is guaranteed over the specified temperature range. 4. clock speeds of less than 1.0 mhz, at temperatures >100 c will degrade dnl performance. 5. wideband noise aliased into the baseband. referred to the input. *refer to parameter definitions (immediately following the pin descriptions at the end of this data sheet). specifications are subject to change without notice. 2 ds45f2
cs5101a notes: 6. applies only in the track mode. when converting or calibrating, input capacitance will not exceed 30 pf. 7. conversion time scales directly to the master clock speed. the times shown are for synchronous, internal loopback (frn mode) with 8.0 mhz clkin. in pdt, rbt, and ssc modes, asynchronous delay between the falling edge of hold and the start of conversion may add to the apparent conversion time. this delay will not exceed 1.5 master clock cycles + 10 ns. in pdt, rbt, and ssc modes, clkin can be increased as long as the hold sample rate is 100 khz max. 8. the cs5101a requires 6 clock cycles of coarse charge, followed by a minimum of 1.125 m s of fine charge. frn mode allows 9 clock cycles for fine charge which provides for the minimum 1.125 m s with an 8 mhz clock, however; in pdt, rbt, or ssc modes, at clock frequencies of 8 mhz or less, fine charge may be less than 9 clock cycles. this reflects the typ. specification (6 clock cycles + 1.125 m s). 9. throughput is the sum of the acquisition and conversion times. it will vary in accordance with conditions affecting acquisition and conversion times, as described above. 10. all outputs unloaded. all inputs at vd+ or dgnd. 11. power consumption in the sleep mode applies with no master clock applied (clkin held high or low). 12. with 300 mv p-p, 1 khz ripple applied to each supply separately in the bipolar mode. rejection improves by 6 db in the unipolar mode to 90 db. figure 23 shows a plot of typical power supply rejection versus frequency. analog characteristics (continued) cs5101a -j,k cs5101a -a,b cs5101a -s,t parameter* symbol min typ max min typ max min typ max units specified temperature range - 0 to +70 40 to +85 55 to +125 c analog input aperture time - - 25 - - 25 - - 25 - ns aperture jitter - - 100 - - 100 - - 100 - ps input capacitance (note 6) unipolar mode bipolar mode - - - - 320 200 425 265 - - 320 200 425 265 - - 320 200 425 265 pf pf conversion & throughput conversion time (note 7) -8 -16 t c tc - - - - 8.12 16.25 - - - - 8.12 16.25 - - - - 8.12 16.25 m s m s acquisition time (note 8) -8 -16 t a ta - - - 2.6 1.88 3.75 - - - 2.6 1.88 3.75 - - - 2.6 2.88 3.75 m s m s throughput (note 9) -8 -16 f tp f tp 100 50 - - - - 100 50 - - - - 100 50 - - - - khz khz power supplies power supply current (note 10) positive analog negative analog (sleep high) positive digital negative digital i a + i a - i d + i d - - - - - 21 -21 11 -11 28 -28 15 -15 - - - - 21 -21 11 -11 28 -28 15 -15 - - - - 21 -21 11 -11 28 -28 15 -15 ma ma ma ma power consumption (notes 10, 11) (sleep high) (sleep low) p do p ds - - 320 1 430 - - - 320 1 430 - - - 320 1 430 - mw mw power supply rejection: (note 12) positive supplies negative supplies psr psr - - 84 84 - - - - 84 84 - - - - 84 84 - - db db ds45f2 3
cs5101a notes: 13. external loading capacitors are required to allow the crystal to oscillate. maximum crystal frequency is 8.0 mhz in frn mode (100 khz sample rate). 14. with a 8 mhz crystal, two 10 pf loading capacitors and a 10 m w parallel resistor (see figure 8). 15. these times are for frn mode. 16. ssh only works correctly if hold falling edge is within +15 to +30 ns of ch1/ 2 edge or if ch1/ 2 edge occurs after hold rises to 64 t clk after hold has fallen. these times are for pdt and rbt modes. 17. when hold goes low, the analog sample is captured immediately. to start conversion, hold must be latched by a falling edge of clkin. conversion will begin on the next rising edge of clkin after hold is latched. if hold is operated synchronous to clkin, the hold pulse width may be as narrow as 150 ns for all clkin frequencies if clkin falls 95 ns after hold falls. this ensures that the hold pulse will meet the minimum specification for t hcf . switching characteristics (t a = t min to t max ; va+, vd+ = 5v 10%; va-, vd- = -5v 10%; inputs: logic 0 = 0v, logic 1 = vd+; c l = 50 pf) parameter symbol min typ max units clkin period (note 4) -8 -16 t clk t clk 108 250 - - 10,000 10,000 ns ns clkin low time t clkl 37.5 - - ns clkin high time t clkh 37.5 - - ns crystal frequency (note 13) -8 -16 f xtal f xtal 2.0 2.0 - - 9.216 4.0 mhz mhz sleep rising to oscillator stable (note 14) - - 2 - ms rst pulse width t rst 150 - - ns rst to stby falling t drrs - 100 - ns rst rising to stby rising t cal - 11,528,160 - t clk ch1/2 edge to trk1, trk2 rising (note 15) t drsh1 -80-ns ch1/2 edge to trk1, trk2 falling (note 15) t dfsh4 - - 68t clk +260 ns hold to ssh falling (note 16) t dfsh2 -60 ns hold to trk1, trk2, falling (note 16) t dfsh1 66t clk - 68t clk +260 ns hold to trk1, trk2, ssh rising (note 16) t drsh - 120 - ns hold pulse width (note 17) t hold 1t clk +20 - 63t clk ns hold to ch1/2 edge (note 16) t dhlri 15 - 64t clk ns hold falling to clkin falling (note 17) t hcf 95 - 1tclk+10 ns 4 ds45f2
analog characteristics (t a = t min to t max ; va+, vd+ = 5v; va-, vd- = -5v; vref = 4.5v; full-scale input sinewave, 200 hz; clkin = 1.6 mhz; f s = 20 khz; bipolar mode; frn mode; ain1 and ain2 tied together, each channel tested separately; analog source impedance = 50 w with 1000pf to agnd unless otherwise specified) cs5102a-j,k cs5102a-a,b cs5102a-s,t parameter* min typ max min typ max min typ max units specified temperature range 0 to +70 -40 to +85 -55 to +125 c accuracy linearity error -j,a,s (note 1) -k,b,t drift (note 2) - - - 0.002 0.001 1/4 0.003 0.0015 - - - - 0.002 0.001 1/4 0.003 0.0015 - - - - 0.002 0.001 1/2 0.004 0.002 - %fs %fs d lsb differential linearity (notes 3, 18) 16 - - 16 - - 16 - - bits full scale error -j,a,s (note 1) -k,b,t drift (note 2) - - - 2 2 1 4 3 - - - - 2 2 1 4 3 - - - - 2 2 2 5 3 - lsb lsb d lsb unipolar offset -j,a,s (note 1) -k,b,t drift (note 2) - - - 1 1 1 4 3 - - - - 1 1 1 4 3 - - - - 1 1 2 5 3 - lsb lsb d lsb bipolar offset -j,a,s (note 1) -k,b,t drift (note 2) - - - 1 1 1 4 3 - - - - 1 1 2 4 3 - - - - 1 1 2 5 3 - lsb lsb d lsb bipolar negative -j,a,s (note 1) full-scale error -k,b,t drift (note 2) - - - 2 2 1 4 3 - - - - 2 2 2 4 3 - - - - 2 2 2 5 3 - lsb lsb d lsb dynamic performance (bipolar mode) peak harmonic or -j,a,s (note 1) spurious noise -k,b,t 96 98 100 102 - - 96 98 100 102 - - 94 98 100 102 - - db db total harmonic distortion -j,a,s -k,b,t - - 0.002 0.001 - - - - 0.002 0.001 - - - - 0.002 0.001 - - % % signal-to-noise ratio (note 1) 0db input -j,a,s -k,b,t -60 db input -j,a,s -k,b,t 87 90 - - 90 92 30 32 - - - - 87 90 - - 90 92 30 32 - - - - 87 90 - - 90 92 30 32 - - - - db db db db noise (note 5) unipolar mode bipolar mode - - 35 70 - - - - 35 70 - - - - 35 70 - - m v rms m v rms note: 18. clock speeds of less than 1.6 mhz, at temperatures >100 c will degrade dnl performance. *refer to parameter definitions (immediately following the pin descriptions at the end of this data sheet). specifications are subject to change without notice. cs5102a ds45f2 5
notes: 19. conversion time scales directly to the master clock speed. the times shown are for synchronous, internal loopback (frn mode). in pdt, rbt, and ssc modes, asynchronous delay between the falling edge of hold and the start of conversion may add to the apparent conversion time. this delay will not exceed 1 master clock cycle + 140 ns. 20. the cs5102a requires 6 clock cycles of coarse charge, followed by a minimum of 5.625 m s of fine charge. frn mode allows 9 clock cycles for fine charge which provides for the minimum 5.625 m s with an 1.6 mhz clock, however; in pdt, rbt, or ssc modes, at clock frequencies less than 1.6 mhz, fine charge may be less than 9 clock cycles. 21. throughput is the sum of the acquisition and conversion times. it will vary in accordance with conditions affecting acquisition and conversion times, as described above. 22. all outputs unloaded. all inputs at vd+ or dgnd. see table below for power dissipation vs. clock frequency. 23. with 300 mv p-p, 1 khz ripple applied to each supply separately in the bipolar mode. rejection improves by 6 db in the unipolar mode to 90 db. figure 23 shows a plot of typical power supply rejection versus frequency. cs5102a analog characteristics (continued) cs5102a -j,k cs5102a -a,b cs5102a -s,t parameter* symbol min typ max min typ max min typ max units specified temperature range - 0 to +70 40 to +85 -55 to +125 c analog input aperture time - - 30 - - 30 - - 30 - ns aperture jitter - - 100 - - 100 - - 100 - ps input capacitance (note 6) unipolar mode bipolar mode - - - - 320 200 425 265 - - 320 200 425 265 - - 320 200 425 265 pf pf conversion & throughput conversion time (note 19) t c - - 40.625 - - 40.625 - - 40.625 m s acquisition time (note 20) t a - - 9.375 - - 9.375 - - 9.375 m s throughput (note 21) f tp 20 - - 20 - - 20 - - khz power supplies power supply current (note 22) positive analog negative analog (sleep high) positive digital negative digital i a + i a - i d + i d - - - - - 2.4 -2.4 2.5 -1.5 3.5 -3.5 3.5 -2.5 - - - - 2.4 -2.4 2.5 -1.5 3.5 -3.5 3.5 -2.5 - - - - 2.4 -2.4 2.5 -1.5 3.5 -3.5 3.5 -2.5 ma ma ma ma power consumption (notes 11, 22) (sleep high) (sleep low) p do p ds - - 44 1 65 - - - 44 1 65 - - - 44 1 65 - mw mw power supply rejection: (note 23) positive supplies negative supplies psr psr - - 84 84 - - - - 84 84 - - - - 84 84 - - db db typ. power (mw) clkin (mhz) 34 0.8 37 1.0 39 1.2 41 1.4 44 1.6 6 ds45f2
switching characteristics (t a = t min to t max ; va+, vd+ = 5v 10%; va-, vd- = -5v 10%; inputs: logic 0 = 0v, logic 1 = vd+; c l = 50 pf) parameter symbol min typ max units clkin period (note 18,24) t clk 0.5 - 10 m s clkin low time t clkl 200 - - ns clkin high time t clkh 200 - - ns crystal frequency (note 24, 25) f xtal 0.9 1.6 2.0 mhz sleep rising to oscillator stable (note 26) - - 20 - ms rst pulse width t rst 150 - - ns rst to stby falling t drrs - 100 - ns rst rising to stby rising t cal - 2,882,040 - t clk ch1/2 edge to trk1, trk2 rising (note 27) t drsh1 -80-ns ch1/2 edge to trk1, trk2 falling (note 27) t dfsh4 - - 68t clk +260 ns hold to ssh falling (note 28) t dfsh2 -60 ns hold to trk1, trk2, falling (note 28) t dfsh1 66t clk - 68t clk +260 ns hold to trk1, trk2, ssh rising (note 28) t drsh - 120 - ns hold pulse width (note 29) t hold 1t clk +20 - 63t clk ns hold to ch1/2 edge (note 28) t dhlri 15 - 64t clk ns hold falling to clkin falling (note 29) t hcf 55 - 1tclk+10 ns note: 24. minimum clkin period is 0.625 m s in frn mode (20 khz sample rate). at temperatures >+85 c, and with clock frequencies <1.6 mhz, analog performance may be degraded. 25. external loading capacitors are required to allow the crystal to oscillate. maximum crystal frequency is 1.6 mhz in frn mode (20 khz sample rate). 26. with a 2.0 mhz crystal, two 33 pf loading capacitors and a 10 m w parallel resistor (see figure 8). 27. these times are for frn mode. 28. ssh only works correctly if hold falling edge is within +15 to +30 ns of ch1/ 2 edge or if ch1/ 2 edge occurs after hold rises to 64 t clk after hold has fallen. these times are for pdt and rbt modes. 29. when hold goes low, the analog sample is captured immediately. to start conversion, hold must be latched by a falling edge of clkin. conversion will begin on the next rising edge of clkin after hold is latched. if hold is operated synchronous to clkin, the hold pulse width may be as narrow as 150 ns for all clkin frequencies if clkin falls 55 ns after hold falls. this ensures that the hold pulse will meet the minimum specification for t hcf . cs5102a ds45f2 7
dhlri t hold t ch1/2 hold clkin t hcf hold rst t cal t drrs t rst stby dfsh4 t ch1/2 drsh1 t hold ssh,trk1,trk2 dfsh2 t drsh t dfsh1 t trk1,trk2 trk1,trk2 trk1,trk2 ssh/sdl control output timing reset and calibration timing channel selection timing a. frn mode b. pdt, rbt mode start conversion timing cs5101a cs5102a 8 ds45f2
switching characteristics (continued) parameter symbol min typ max units pdt and rbt modes sclk input pulse period t sclk 200 - - ns sclk input pulse width low t sclkl 50 - - ns sclk input pulse width high t sclkh 50 - - ns sclk input falling to sdata valid t dss - 100 150 ns hold falling to sdata valid pdt mode t dhs - 140 230 ns trk1, trk2 falling to sdata valid (note 30) t dts - 65 125 ns frn and ssc modes sclk output pulse width low t slkl -2t clk -t clk sclk output pulse width high t slkh -2t clk -t clk sdata valid before rising sclk t ss 2t clk -100 - - ns sdata valid after rising sclk t sh 2t clk -100 - - ns sdl falling to 1st rising sclk t rsclk -2t clk -ns last rising sclk to sdl rising cs5101a cs5102a t rsdl t rsdl - - 2t clk 2tclk 2tclk+165 2t clk +200 ns ns hold falling to 1st falling sclk cs5101a cs5102a t hfs thfs 6tclk 6t clk - - 8t clk +165 8t clk +200 ns ns ch1/2 edge to 1st falling sclk t chfs -7tclk-t clk note: 30. only valid for trk1, trk2 falling when sclk is low. if sclk is high when trk1, trk2 falls, then sdata is valid t dss time after the next falling sclk. digital characteristics (t a = t min to t max ; va+, vd+ = 5v 10%; va-, vd- = 5v 10%) parameter symbol min typ max units calibration memory retention (note 31) power supply voltage va+ and vd+ v mr 2.0 - - v high-level input voltage v ih 2.0 - - v low-level input voltage v il --0.8v high-level output voltage (note 32) v oh (vd+)-1.0 - - v low-level output voltage i out = 1.6 ma v ol --0.4v input leakage current i in --10 m a digital output pin capacitance c out -9-pf notes: 31. va- and vd- can be any value from zero to -5v for memory retention. neither va- or vd- should be allowed to go positive. ain1, ain2 or vref must not be greater than va+ or vd+. this parameter is guaranteed by characterization. 32. i out = -100 m a. this specification guarantees ttl compatibility (v oh = 2.4v @ iout = -40 m a). cs5101a cs5102a ds45f2 9
sclkl t sclkh t dss t sdata sclk sclk msb dhs t hold sdata msb sdata dts t sclk t dss t msb-1 sclk trk1, trk2 ss t msb sclk sh t sdata slkh t slkl t dss t chfs t ch1/2 hold hfs t ssh/sdl rsclk t lsb rsdl t data transmission timing a. sclk input (rbt and pdt mode) b. sclk output (ssc and frn modes) a. pipelined data transmission (pdt) b. register burst transmission (rbt) mode serial data timing cs5101a cs5102a 10 ds45f2
notes: 35. in addition, vd+ must not be greater than (va+) +0.3v 36. transient currents of up to 100 ma will not cause scr latch-up. *warning: operation beyond these limits may result in permanent damage to the device. notes: 33. all voltages with respect to ground. 34. the cs5101a and cs5102a can accept input voltages up to the analog supplies (va+ and va-). they will produce an output of all 1s for inputs above vref and all 0s for inputs below agnd in unipolar mode and -vref in bipolar mode, with binary coding (code = low). recommended operating conditions (agnd, dgnd = 0v, see note 33) parameter symbol min typ max units dc power supplies: positive digital negative digital positive analog negative analog vd+ vd- va+ va- 4.5 -4.5 4.5 -4.5 5.0 -5.0 5.0 -5.0 va+ -5.5 5.5 -5.5 v v v v analog reference voltage vref 2.5 4.5 (va+)-0.5 v analog input voltage: (note 34) unipolar bipolar v ain v ain agnd -vref - - vref vref v v absolute maximum ratings* (agnd, dgnd = 0v, all voltages with respect to ground) parameter symbol min typ max units dc power supplies: positive digital (note 35) negative digital positive analog negative analog vd+ vd- va+ va- -0.3 0.3 -0.3 0.3 - - - - 6.0 -6.0 6.0 -6.0 v v v v input current, any pin except supplies (note 36) i in -- 10 ma analog input voltage (ain and vref pins) v ina (va-)-0.3 - (va+)+0.3 v digital input voltage v ind -0.3 - (va+)+0.3 v ambient operating temperature t a -55 - 125 c storage temperature t stg -65 - 150 c ambient operating temperature t a -55 - 125 c storage temperature t stg -65 - 150 c cs5101a cs5102a ds45f2 11
general description the cs5101a and cs5102a are 2-channel, 16- bit a/d converters. the devices include an inherent sample/hold and an on-chip analog switch for 2-channel operation. both channels can thus be sampled and converted at rates up to 50 khz each (cs5101a) or 10 khz each (cs5102a). alternatively, each of the devices can be operated as a single channel adc operat- ing at 100 khz (cs5101a) or 20 khz (cs5102a). both the cs5101a and cs5102a can be config- ured to accept either unipolar or bipolar input ranges, and data is output serially in either binary or 2s complement coding. the devices can be configured in 3 different output modes, as well as an internal, synchronous loopback mode. the cs5101a and cs5102a provide coarse charge/fine charge control, to allow accurate tracking of high-slew signals. theory of operation the cs5101a and cs5102a implement the suc- cessive approximation algorithm using a charge redistribution architecture. instead of the tradi- tional resistor network, the dac is an array of binary-weighted capacitors. all capacitors in the array share a common node at the comparators input. as shown in figure 1, their other terminals are capable of being connected to agnd, vref, or ain (1 or 2). when the device is not calibrat- ing or converting, all capacitors are tied to ain. switch s1 is closed and the charge on the array, tracks the input signal. when the conversion command is issued, switch s1 opens. this traps the charge on the compara- tor side of the capacitor array and creates a floating node at the comparators input. the con- version algorithm operates on this fixed charge, and the signal at the analog input pin is ignored. in effect, the entire dac capacitor array serves as analog memory during conversion much like a hold capacitor in a sample/hold amplifier. the conversion consists of manipulating the free plates of the capacitor array to vref and agnd to form a capacitive divider. since the charge at the floating node remains fixed, the voltage at that point depends on the proportion of capaci- tance tied to vref versus agnd. the successive-approximation algorithm is used to find the proportion of capacitance, which when connected to the reference will drive the voltage at the floating node to zero. that binary fraction of capacitance represents the converters digital output. ain c c/2 c/32,768 msb lsb bit 15 bit 14 bit 13 bit 0 c = c + c/2 + c/4 + c/8 + ... c/32,768 tot dummy c/32,768 s1 c/4 fine vref agnd coarse coarse fine coarse fine + - + - + - + - figure 1. coarse charge input buffers and charge redistribution dac cs5101a cs5102a 12 ds45f2
calibration the ability of the cs5101a or the cs5102a to convert accurately to 16-bits clearly depends on the accuracy of its comparator and dac. each device utilizes an "auto-zeroing" scheme to null errors introduced by the comparator. all offsets are stored on the capacitor array while in the track mode and are effectively subtracted from the input signal when a conversion is initiated. auto-zeroing enhances power supply rejection at frequencies well below the conversion rate. to achieve 16-bit accuracy from the dac, the cs5101a and cs5102a use a novel self-calibra- tion scheme. each bit capacitor shown in figure 1 actually consists of several capacitors in parallel which can be manipulated to adjust the overall bit weight. an on-chip micro controller precisely adjusts each capacitor with a resolution of 18 bits. the cs5101a and cs5102a should be reset upon power-up, thus initiating a calibration cycle. the device then stores its calibration coefficients in on-chip sram. when the cs5101a and cs5102a are in power-down mode ( sleep low), they retain the calibration coefficients in memory, and need not be recalibrated when nor- mal operation is resumed. operation overview monolithic design and inherent sampling archi- tecture make the cs5101a and cs5102a extremely easy to use. initiating conversions a falling transition on the hold pin places the input in the hold mode and initiates a conversion cycle. the charge is trapped on the capacitor ar- ray the instant hold goes low. the device will complete conversion of the sample within 66 master clock cycles, then automatically return to the track mode. after allowing a short time for acquisition, the device will be ready for another conversion. in contrast to systems with separate track-and- holds and a/d converters, a sampling clock can simply be connected to the hold input. the duty cycle of this clock is not critical. the hold input is latched internally by the master clock, so it need only remain low for 1/f clk + 20 ns, but no longer than the minimum conversion time minus two master clocks or an additional conversion cy- cle will be initiated with inadequate time for acquisition. in free run mode, sckmod = outmod = 0, the device will convert at a rate of clkin/80, and the hold input is ignored. as with any high-resolution a-to-d system, it is recommended that sampling is synchronized to the master system clock in order to minimize the effects of clock feedthrough. however, the cs5101a and cs5102a may be operated entirely asynchronous to the master clock if necessary. tracking the input upon completing a conversion cycle the cs5101a and cs5102a immediately return to the track mode. the ch1/ 2 pin directly controls the input switch, and therefore directly deter- mines which channel will be tracked. ideally, the ch1/ 2 pin should be switched during the conver- sion cycle, thereby nullifying the input mux switching time, and guaranteeing a stable input at the start of acquisition. if, however, the ch1/ 2 control is changed during the acquisition phase, adequate coarse charge and fine charge time must be allowed before initiating conversion. when the cs5101a or the cs5102a enters track- ing mode, it uses an internal input buffer amplifier to provide the bulk of the charge on the capacitor array (coarse-charge), thereby reducing the current load on the external analog circuitry. coarse-charge is internally initiated for 6 clock cycles at the end of every conversion. the buffer cs5101a cs5102a ds45f2 13
amplifier is then bypassed, and the capacitor ar- ray is directly connected to the input. this is referred to as fine-charge, during which the charge on the array is allowed to accurately settle to the input voltage (see figure 10). with a full scale input step, the coarse-charge in- put buffer of the cs5101a will charge the capacitor array within 1% in 650 ns. the con- verter timing allows 6 clock cycles for coarse charge settling time. when the cs5101a switches to fine-charge mode, its slew rate is somewhat reduced. in fine-charge, the cs5101a can slew at 2 v/ m s in unipolar mode. in bipolar mode, only half the capacitor array is connected to the analog input, so the cs5101a can slew at 4v/ m s. with a full scale input step, the coarse-charge in- put buffer of the cs5102a will charge the capacitor array within 1% in 3.75 m s. the con- verter timing allows 6 clock cycles for coarse charge settling time. when in fine-charge mode, the cs5102a can slew at 0.4 v/ m s in unipolar mode; and at 0.8 v/ m s in bipolar mode. acquisition of fast slewing signals can be has- tened if the voltage change occurs during or immediately following the conversion cycle. for instance, in multiple channel applications (using either the devices internal channel selector or an external mux), channel selection should occur while the cs5101a or the cs5102a is convert- ing. multiplexer switching and settling time is thereby removed from the overall throughput equation. if the input signal changes drastically during the acquisition period (such as changing the signal source), the device should be in coarse-charge for an adequate period following the change. the cs5101a and cs5102a can be forced into coarse-charge by bringing crs/ fin high. the buffer amplifier is engaged when crs/ fin is high, and may be switched in any number of times during tracking. if crs/ fin is held low, the cs5101a and cs5102a will only coarse- charge for the first 6 clock cycles following a conversion, and will stay in fine-charge until hold goes low. to get an accurate sample using the cs5101a, at least 750 ns of coarse-charge, followed by 1.125 m s of fine-charge is required before initiating a conversion. if coarse charge is not invoked, then up to 25 m s should be allowed after a step change input for proper acquisition. to get an accurate sample using the cs5102a, at least 3.75 m s of coarse-charge, followed by 5.625 m s of fine-charge is required before initiat- ing a conversion (see figure 2). if coarse charge is not invoked, then up to 125 m s should be al- lowed after a step change input for proper acquisition. the crs/ fin pin must be low prior to hold becoming active and be held low dur- ing conversion. master clock the cs5101a and cs5102a can operate either from an externally-supplied master clock, or from their own crystal oscillator (with a crystal). to enable the internal crystal oscillator, simply tie a crystal across the xout and clkin pins and add 2 capacitors and a resistor, as shown on the system connection diagram in figure 8. calibration and conversion times directly scale to the master clock frequency. the cs5101a-8 can operate with clock or crystal frequencies up to 9.216 mhz (8.0 mhz in frn mode). this allows maximum throughput of up to 50 khz per chan- nel in dual-channel operation, or 100 khz in a single channel configuration. the cs5101a-16 can accept a maximum clock speed of 4 mhz, with corresponding thr oughput of 50 khz. the cs5102a can operate with clock or crystal frequen- cies up to 2.0 mhz (1.6 mhz in frn mode). this allows maximum throughput of up to 10 khz per channel in dual-channel operation, or 20 khz in a single channel configuration. for 16 bit performance a 1.6 mhz clock is recommended. this 1.6 mhz cs5101a cs5102a 14 ds45f2
clock yields a maximum throughput of 20 khz in a single channel configuration. asynchronous sampling considerations when hold goes low, the analog sample is cap- tured immediately. the hold signal is latched by the next falling edge of clkin, and conver- sion then starts on the subsequent rising edge. if hold is asynchronous to clkin, then there will be a 1.5 clkin cycle uncertainty as to when conversion starts. considering the cs5101a with an 8 mhz clkin, with a 100 khz hold signal, then this 1.5 clkin uncertainty will result in a 1.5 clkin period possible reduction in fine charge time for the next conversion. this reduced fine charge time will be less than the minimum specification. if the clkin fre- quency is increased slightly (for example, to 8.192 mhz) then sufficient fine charge time will always occur. the maximum frequency for clkin is specified at 9.216 mhz; it is recom- mended that for asynchronous operation at 100 khz, clkin should be between 8.192 mhz and 9.216 mhz. analog input range/coding format the reference voltage directly defines the input voltage range in both the unipolar and bipolar configurations. in the unipolar configuration (bp/ up low), the first code transition occurs 0.5 lsb above agnd, and the final code transition occurs 1.5 lsbs below vref. in the bipolar configuration (bp/ up high), the first code transi- tion occurs 0.5 lsb above -vref and the last transition occurs 1.5 lsbs below +vref. the cs5101a and cs5102a can output data in either 2s complement, or binary format. if the code pin is high, the output is in 2s comple- ment format with a range of -32,768 to +32,767. if the code pin is low, the output is in binary format with a range of 0 to +65,535. see table 1 for output coding. clkin crs/fin internal status conv. coarse fine chg. coarse fine chg. conv. trk1 or trk2 hold min: 1.125 m s* 6 clk 2 clk min: 750 ns* 3.75 m s** 5.625 m s** * applies to 5101a ** applies to 5102a figure 2. coarse-charge/fine-charge control unipolar input voltage offset binary two?s complement bipolar input voltage >(vref-1.5 lsb) ffff 7fff >(vref-1.5 lsb) vref-1.5 lsb ffff fffe 7fff 7ffe vref-1.5 lsb vref/2-0.5 lsb 8000 7fff 0000 ffff -0.5 lsb +0.5 lsb 0001 0000 8001 8000 -vref+0.5 lsb <(+0.5 lsb) 0000 8000 <(-vref+0.5 lsb) table 1. output coding cs5101a cs5102a ds45f2 15
output mode control the cs5101a and cs5102a can be configured in three different output modes, as well as an in- ternal, synchronous loop-back mode. this allows great flexibility for design into a wide variety of systems. the operating mode is selected by set- ting the states of the sckmod and outmod pins. in all modes, data is output on sdata, starting with the msb. each subsequent data bit is updated on the falling edge of sclk. when sckmod is high, sclk is an input, al- lowing the data to be clocked out with an external serial clock at rates up to 5 mhz. addi- tional clock edges after #16 will clock out logic 1s on sdata. tying sckmod low reconfig- ures sclk as an output, and the converter clocks out each bit as its determined during the conver- sion process, at a rate of 1/4 the master clock speed. table 2 shows an overview of the different states of sckmod and outmod, and the cor- responding output modes. pipelined data transmission (pdt) pdt mode is selected by tying both sckmod and outmod high. in pdt mode, the sclk pin is an input. data is registered during conver- sion, and output during the following conversion cycle. hold must be brought low, initiating an- other conversion, before data from the previous conversion is available on sdata. if all the data has not been clocked out before the next falling edge of hold, the old data will be lost (figure 3). figure 3. pipelined data transmission mode (pdt) clkin (i) hold (i) internal status sclk (i) sdata (o) ch1/2 (i) d15 d14 d1 d0 (ch. 1) trk1 (o) trk2 (o) ssh/sdl (o) converting ch. 2 d15 d14 d1 d0 (ch. 2) converting ch. 1 d15 68 72 76 0 4 8 64687276 4 8 64 60 60 00 tracking ch. 1 tracking ch. 2 sclk input output input output outmod 0 1 0 1 sckmod 0 1 0 1 mode pdt rbt ssc frn input input input output ch1/2 x input input input hold table 2. serial output modes cs5101a cs5102a 16 ds45f2
d15 d14 d1 d0 (ch. 1) clkin (i) hold (i) internal status sclk (o) sdata (o) ch1/2 (i) d15 d14 d1 d0 (ch. 2) trk1 (o) trk2 (o) ssh/sdl (o) 68 72 76 048 64 68 72 76 4 864 0 0 6 6 converting ch. 2 tracking ch. 1 converting ch. 1 tracking ch. 2 clkin (i) hold (i) internal status sclk (i) sdata (o) ch1/2 (i) trk1 (o) trk2 (o) ssh/sdl (o) converting ch. 2 converting ch. 1 d0 d0 channel 2 data channel 1 data 04 4 0 0 64 68 72 64 68 72 tracking ch. 1 tracking ch. 2 clkin (i) d15 d1 d0 (ch. 1) internal status sclk (o) sdata (o) ch1/2 (o) d15 d1 d0 (ch. 2) trk1 (o) trk2 (o) ssh/sdl (o) 68 72 76 048 64 68 72 76 4 8 64 0 0 7 69 7 69 converting ch. 2 tracking ch. 1 converting ch. 1 tracking ch. 2 figure 5. synchronous self-clocking mode (ssc) figure 4. registered burst transmission mode (rbt) figure 6. free run mode (frn) cs5101a cs5102a ds45f2 17
registered burst transmission (rbt) rbt mode is selected by tying sckmod high, and outmod low. as in pdt mode, sclk is an input, however data is available immediately following conversion, and may be clocked out the moment trk1 or trk2 falls. the falling edge of hold clears the output buffer , so any unread data will be lost. a new conversion may be initiated before all the data has been clocked out if the unread data bits are not important (figure 4). synchronous self-clocking (ssc) ssc mode is selected by tying sckmod low, and outmod high. in ssc mode, sclk is an output, and will clock out each bit of the data as its being converted. sclk will remain high be- tween conversions, and run at a rate of 1/4 the master clock speed for 16 low pulses during con- version (figure 5). the ssh/sdl goes low coincident with the first falling edge of sclk, and returns high 2 clkin cycles after the last rising edge of sclk. this signal frames the 16 data bits and is useful for interfacing to shift registers (e.g. 74hc595) or to dsp serial ports. free run (frn) free run is the internal, synchronous loopback mode. frn mode is selected by tying sckmod and outmod low. sclk is an output, and op- erates exactly the same as in the ssc mode. in free run mode, the converter initiates a new conversion every 80 master clock cycles, and al- ternates between channel 1 and channel 2. hold is disabled, and should be tied to either vd+ or dgnd. ch1/ 2 is an output, and will change at the start of each new conversion cycle, indicating which channel will be tracked after the current conversion is finished (figure 6). the ssh/sdl goes low coincident with the first falling edge of sclk, and returns high 2 clkin cycles after the last rising edge of sclk. this signal frames the 16 data bits and is useful for interfacing to shift registers (e.g. 74hc595) or to dsp serial ports. system design with the cs5101a and cs5102a figure 7 shows a general system connection dia- gram for the cs5101a and cs5102a. digital circuit connections when ttl loads are utilized the potential for crosstalk between digital and analog sections of the system is increased. this crosstalk is due to high digital supply and signal currents arising from the ttl drive current required of each digi- tal output. connecting cmos logic to the digital outputs is recommended. suitable logic families include 4000b, 74hc, 74ac, 74act, and 74hct. system initialization upon power up, the cs5101a and cs5102a must be reset to guarantee a consistent starting condition and initially calibrate the device. due to each devices low power dissipation and low temperature drift, no warm-up time is required before reset to accommodate any self-heating ef- fects. however, the voltage reference input should have stabilized to within 0.25% of its final value before rst rises to guarantee an accurate calibration. later, the cs5101a and cs5102a may be reset at any time to initiate a single full calibration. when rst is brought low all internal logic clears. when rst returns high on the cs5101a, a calibration cycle begins which takes 11,528,160 master clock cycles to complete (approximately 1.4 seconds with an 8 mhz master clock). the cs5101a cs5102a 18 ds45f2
calibration cycle on the cs5102a takes 2,882,040 master clock cycles to complete (ap- proximately 1.8 seconds with a 1.6 mhz master clock). the cs5101as and cs5102as stby output remains low throughout the calibration se- quence, and a rising transition indicates the device is ready for normal operation. while cali- brating, the cs5101a and cs5102a will ignore changes on the hold input. to perform the reset function, a simple power-on reset circuit can be built using a resistor and ca- pacitor as shown in figure 8. the resistor should be less than or equal to 10 k w . the system power supplies, voltage reference, and clock should all be established prior rst rising. single-channel operation the cs5101a and cs5102a can alternatively be used to sample one channel by tying the ch1/ 2 input high or low. the unused ain pin should be tied to the analog input signal or to agnd. (if operating in free run mode, ain1 and ain2 must va+ vd+ 10 +5va + 4.7 m f 0.1 m f + 1 m f 0.1 m f 23 1 10 ++ -5va 4.7 m f 0.1 m f1 m f 0.1 m f 0.1 m f 21 va- vd- refbuf 25 7 clkin xout 6 dgnd sleep stby trk1 trk2 ssh/sdl sdata rst ch1/2 sclk hold 10 m 3 4 ext clock c2 = c1 10 28 5 8 9 11 15 2 13 14 12 data interface control logic crs/fin 16 17 27 18 26 code sckmod outmod bp/up vd+ mode control ain1 ain2 19 24 50 1 nf 50 1 nf analog sources vref agnd 20 22 voltage reference * * * for best dynamic s/(n+d) performance. npo npo unused logic inputs should be tied to vd+ or dgnd. c1 cs5101a or cs5102a xtal xtal & c1 table cs5101a frn cs5102a frn xtal 8.0 mhz 8.192 mhz 1.6 mhz c1, c2 10 pf 10 pf 30 pf 30 pf 2.0 mhz 1.6 mhz or tst pdt, rbt, ssc pdt, rbt, ssc figure 7. cs5101a/cs5102a system connection diagram cs5101a cs5102a ds45f2 19
be tied to the same source, as ch1/ 2 is reconfig- ured as an output.) analog circuit connections most popular successive approximation a/d con- verters generate dynamic loads at their analog connections. the cs5101a and cs5102a inter- nally buffer all analog inputs (ain1, ain2, vref, and agnd) to ease the demands placed on external circuitry. however, accurate system operation still requires careful attention to details at the design stage regarding source impedances as well as grounding and decoupling schemes. reference considerations an application note titled " voltage references for the cs501x series of a/d converters " is avail- able for the cs5101a and cs5102a. in addition to working through a reference circuit design example, it offers several built-and-tested reference circuits. during conversion, each capacitor of the cali- brated capacitor array is switched between vref and agnd in a manner determined by the suc- cessive-approximation algorithm. the charging and discharging of the array results in a current load at the reference. the cs5101a and cs5102a each include an internal buffer ampli- fier to minimize the external reference circuits drive requirement and preserve the references in- tegrity. whenever the array is switched during conversion, the buffer is used to coarse-charge the array thereby providing the bulk of the neces- sary charge. the appropriate array capacitors are then switched to the unbuffered vref pin to avoid any errors due to offsets and/or noise in the buffer. the external reference circuitry need only pro- vide the residual charge required to fully charge the array after coarse-charging from the buffer. this creates an ac current load as the cs5101a and cs5102a sequence through conversions. the reference circuitry must have a low enough out- put impedance to drive the requisite current without changing its output voltage significantly. as the analog input signal varies, the switching sequence of the internal capacitor array changes. the current load on the external reference cir- cuitry thus varies in response with the analog input. therefore, the external reference must not exhibit significant peaking in its output imped- ance characteristic at signal frequencies or their harmonics. a large capacitor connected between vref and agnd can provide sufficiently low output im- pedance at the high end of the frequency spectrum, while almost all precision references exhibit extremely low output impedance at dc. the presence of large capacitors on the output of some voltage references, however, may cause peaking in the output impedance at intermediate frequencies. care should be exercised to ensure that significant peaking does not exist or that some form of compensation is provided to elimi- nate the effect. the magnitude of the current load on the external reference circuitry will scale to the master clock frequency. at the full-rated 9.216 mhz clock (cs5101a), the reference must supply a maxi- mum load current of 20 m a peak-to-peak (2 m a typical). an output impedance of 2 w will there- fore yield a maximum error of 40 m v. a t t h e full-rated 2.0 mhz clock (cs5102a), the refer- c r +5v 1n4148 cs5102a cs5101a or vd+ rst ____ figure 8. power-up reset circuit cs5101a cs5102a 20 ds45f2
ence must supply a maximum load current of 5 m a peak-to-peak (0.5 m a typical). an output impedance of 2 w will therefore yield a maxi- mum error of 10.0 m v. with a 4.5 v reference and lsb size of 138 m v this would insure approxi- mately 1/14 lsb accuracy. a 10 m f capacitor exhibits an impedance of less than 2 w at fre- quencies greater than 16 khz. a high-quality tantalum capacitor in parallel with a smaller ce- ramic capacitor is recommended. peaking in the references output impedance can occur because of capacitive loading at its output. any peaking that might occur can be reduced by placing a small resistor in series with the capaci- tors. the equation in figure 9 can be used to help calculate the optimum value of r for a particular reference. the term "f peak " is the frequency of the peak in the output impedance of the reference before the resistor is added. the cs5101a and cs5102a can operate with a wide range of reference voltages, but signal-to- noise performance is maximized by using as wide a signal range as possible. the recom- mended reference voltage is 4.5 volts. the cs5101a and cs5102a can actually accept ref- erence voltages up to the positive analog supply. however, the buffers offset may increase as the reference voltage approaches va+ thereby in- creasing external drive requirements at vref. a 4.5v reference is the maximum reference voltage recommended. this allows 0.5v headroom for the internal reference buffer. also, the buffer en- lists the aid of an external 0.1 m f ceramic capacitor which must be tied between its output, refbuf, and the negative analog supply, va-. for more information on references, consult "ap- plication note: voltage references for the cs501x series of a/d converters ". analog input connection the analog input terminal functions similarly to the vref input after each conversion when switching into the track mode. during the first six master clock cycles in the track mode, the buffered version of the analog input is used for coarse-charging the capacitor array. an additional period is required for fine-charging directly from ain to obtain the specified accuracy. figure 10 shows this operation. during coarse-charge the charge on the capacitor array first settles to the buffered version of the analog input. this voltage may be offset from the actual input voltage. dur- ing fine-charge, the charge then settles to the accurate unbuffered version. 21 20 23 vref refbuf va- 0.1 m f 10 m f -5v 0.01 m f r* +v ee cs5101a or cs5102a ref v figure 9. reference connections r= 1 2 p (c 1 + c 2 ) f peak acquisition time (us) internal charge error (lsb's) +200 0 -100 -400 +100 -200 -300 fine-charge coarse-charge 0.25 0.5 0.75 1.0 1.0 2.0 3.0 4.0 8 mhz clock 2.0 mhz clock figure 10. charge settling time (8 and 2.0 mhz clocks) cs5101a cs5102a ds45f2 21
fine-charge settling is specified as a maximum of 1.125 m s (cs5101a) or 5.625 m s (cs5102a) for an analog source impedance of less than 50 w . in addition, the comparator requires a source imped- ance of less than 400 w around 2 mhz for stability. the source impedance can be effectively reduced at high frequencies by adding capaci- tance from ain to ground (typically 200 pf). however, high dc source resistances will increase the inputs rc time constant and extend the nec- essary acquisition time. for more information on input amplifiers, consult the application note: buffer amplifiers for the cs501x series of a/d converters . sleep mode operation the cs5101a and cs5102a include a sleep pin. when sleep is active (low) each device will dissipate very low power to retain its calibra- tion memory when the device is not sampling. it does not require calibration after sleep is made inactive (high). when coming out of sleep, sampling can begin as soon as the oscillator starts (time will depend on the particular oscillator components) and the refbuf capacitor is charged (which takes about 3 ms for the cs5101a, 50 ms for the cs5102a). to achieve minimum start-up time, use an external clock and leave the voltage reference powered-up. connect a resistor (2 k w ) between pins 20 and 21 to keep the refbuf capacitor charged. conversion can then begin as soon as the a/d circuitry has stabi- lized and performed a track cycle. to retain calibration memory while sleep is ac- tive (low) va+ and vd+ must be maintained at greater than 2.0v. va- and vd- can be allowed to go to 0 volts. the voltages into va- and vd- cannot just be "shut-off" as these pins cannot be allowed to float to potentials greater than agnd/dgnd. if the supply voltages to va- and vd- are removed, use a transistor switch to short these to the power supply ground while in sleep mode. grounding and power supply decoupling the cs5101a and cs5102a use the analog ground connection, agnd, only as a reference voltage. no dc power currents flow through the agnd connection, and it is completely inde- pendent of dgnd. however, any noise riding on the agnd input relative to the systems analog ground will induce conversion errors. therefore, both the analog input and reference voltage should be referred to the agnd pin, which should be used as the entire systems analog ground reference. the digital and analog supplies are isolated within the cs5101a and cs5102a and are pinned out separately to minimize coupling be- tween the analog and digital sections of the chip. all four supplies should be decoupled to their re- spective grounds using 0.1 m f ceramic capacitors. if significant low-frequency noise is present on the supplies, tantalum capacitors are recom- mended in parallel with the 0.1 m f capacitors. the positive digital power supply of the cs5101a and cs5102a must never exceed the positive analog supply by more than a diode drop or the cs5101a and cs5102a could experience permanent damage. if the two supplies are de- rived from separate sources, care must be taken that the analog supply comes up first at power- up. the system connection diagram (figure 7) shows a decoupling scheme which allows the cs5101a and cs5102a to be powered from a single set of 5v rails. the positive digital sup- ply is derived from the analog supply through a 10 w resistor to avoid the analog supply dropping below the digital supply. if this scheme is util- ized, care must be taken to insure that any digital load currents (which flow through the 10 w resis- tors) do not cause the magnitude of digital supplies to drop below the analog supplies by more than 0.5 volts. digital supplies must always remain above the minimum specification. cs5101a cs5102a 22 ds45f2
as with any high-precision a/d converter, the cs5101a and cs5102a require careful attention to grounding and layout arrangements. however, no unique layout issues must be addressed to properly apply the devices. the cdb5101a evaluation board is available for the cs5101a, and the cdb5102a evaluation board is available for the cs5102a. the availability of these boards avoids the need to design, build, and debug a high-precision pc board to initially characterize the part. each board comes with a socketed cs5101a or cs5102a, and can be reconfigured to simulate any combination of sampling, calibra- tion, master clock, and analog input range conditions. cs5101a and cs5102a performance differential nonlinearity the self-calibration scheme utilized in the cs5101a and cs5102a features a calibration resolution of 1/4 lsb, or 18-bits. this ideally yields dnl of 1/4 lsb, with code widths rang- ing from 3/4 to 5/4 lsbs. traditional laser trimmed adcs have significant differential nonlinearities. appearing as wide and narrow codes, dnl often causes entire sections of the transfer function to be missing. although their affect is minor on s/(n+d) with high ampli- tude signals, dnl errors dominate performance with low-level signals. for instance, a signal 80 db below full-scale will slew past only 6 or 7 codes. half of those codes could be missing with a conventional 16-bit adc which achieves only 14-bit dnl. the most common source of dnl errors in con- ventional adcs is bit weight errors. these can arise due to accuracy limitations in factory trim stations, thermal or physical stresses after calibra- tion, and/or drifts due to aging or temperature variations in the field. bit-weight errors have a drastic effect on a converters ac performance. they can be analyzed as step functions superim- posed on the input signal. since bits (and their errors) switch in and out throughout the transfer curve, their effect is signal dependent. that is, harmonic and intermodulation distortion, as well as noise, can vary with different input conditions. differential nonlinearities in successive-approxi- mation adcs also arise due to dynamic errors in the comparator. such errors can dominate if the converters throughput/sampling rate is too high. the comparator will not be allowed sufficient time to settle during each bit decision in the suc- cessive-approximation algorithm. the worst-case codes for dynamic errors are the major transitions (1/2 fs; 1/4, 3/4 fs; etc.). since dnl effects are most critical with low-level signals, the codes around mid-scale (1/2 fs) are most important. yet those codes are worst-case for dynamic dnl errors! with all linearity calibration performed on-chip to 18-bits, the cs5101a and cs5102a maintain accurate bit weights. dnl errors are dominated by residual calibration errors of 1/4 lsb rather than dynamic errors in the comparator. further- more, all dnl effects on s/(n+d) are buried by white broadband noise. (see figures 17 and 19). figure 11 illustrates the dnl histogram plot of a typical cs5101a at 25 c. figure 12 illustrates the dnl of the cs5101a at 138 c ambient after calibration at 25 c ambient. figures 13 and 14 illustrate the dnl of the cs5102a at 25 c and 138 c ambient, respectively. a histogram test is a statistical method of deriving an a/d converters differential nonlinearity. a ramp is input to the a/d and a large number of samples are taken to insure a high confidence level in the tests result. the number of occurrences for each code is monitored and stored. a perfect a/d converter would have all codes of equal size and therefore equal numbers of occurrences. in the histogram test a code with the average number of occur- rences will be considered ideal (dnl = 0). a cs5101a cs5102a ds45f2 23
0 65,535 cd 32,768 dnl (lsb) +1 0 -1 +1/2 -1/2 t a = 25 c 0 65,535 codes 32,768 dnl (lsb) +1 0 -1 +1/2 -1/2 t a = 138 c, cal @ 25 c 0 65,535 codes 32,768 dnl (lsb) +1 0 -1 +1/2 -1/2 t a = 138 c, cal @ 25 c figure 14. cs5102a dnl plot; ambient temperature at 138 c figure 13. cs5102a dnl plot; ambient temperature at 25 c figure 12. cs5101a dnl plot; ambient temperature at 138 c figure 11. cs5101a dnl plot; ambient temperature at 25 c 0 65,535 codes 32,768 dnl (lsb) +1 0 -1 +1/2 -1/2 t a = 25 c cs5101a cs5102a 24 ds45f2
code with more or less occurrences than average will appear as a dnl of greater or less than zero lsb. a missing code has zero occurrences, and will appear as a dnl of -1 lsb. figures 15 and 16 illustrate the code width distri- bution of the dnl plots shown in figures 11 and 13 respectively. the dnl error distribution plots indicate that the cs5101a and cs5102a cali- brate the majority of their codes to tighter tolerance than the dnl plots in figures 11 and 13 appear to indicate. fft tests and windowing in the factory, the cs5101a and cs5102a are tested using fast fourier transform (fft) tech- niques to analyze the converters dynamic performance. a pure sinewave is applied to the device, and a "time record" of 1024 samples is (thousands) -0.65 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 number of codes with each dnl -0.55 -0.45 -0.35 -0.25 -0.15 -0.05 0 0.05 0.15 0.25 0.35 0.45 0.55 0.65 0 1 16 115 481 3708 15570 25248 15499 3959 714 175 41 5 2 dnl error in lsb # of missing codes: 0 total # of codes analyzed: 65534 figure 15. cs5101a dnl error distribution (thousands) 35 30 25 20 15 10 5 0 number of codes with each dnl -0.45 -0.35 -0.25 -0.15 -0.05 0 0.05 0.15 0.25 0.35 0.45 03 86 1775 16047 31047 14592 1892 88 4 0 dnl error in lsb # of missing codes: 0 total # of codes analyzed: 65534 figure 16. cs5102a dnl error distribution cs5101a cs5102a ds45f2 25
captured and processed. the fft algorithm ana- lyzes the spectral content of the digital waveform and distributes its energy among 512 "frequency bins." assuming an ideal sinewave, distribution of energy in bins outside of the fundamental and dc can only be due to quantization effects and errors in the cs5101a and cs5102a. if sampling is not synchronized to the input sine- wave, it is highly unlikely that the time record will contain an integer number of periods of the input signal. however, the fft assumes that the signal is periodic, and will calculate the spectrum of a signal that appears to have large discontinui- ties, thereby yielding a severely distorted spectrum. to avoid this problem, the time record is multiplied by a window function prior to per- forming the fft. the window function smoothly forces the endpoints of the time record to zero, thereby removing the discontinuities. the effect of the window in the frequency-domain is to con- volute the spectrum of the window with that of the actual input. the quality of the window used for harmonic analysis is typically judged by its highest side- lobe level. a five term window is used in fft testing of the cs5101a and cs5102a. this win- dowing algorithm attenuates the side-lobes to below the noise floor. artifacts of windowing are discarded from the signal-to-noise calculation us- ing the assumption that quantization noise is white. averaging the fft results from ten time records filters the spectral variability that can arise from capturing finite time records without disturbing the total energy outside the fundamen- tal. all harmonics are visible in the plots. for more information on ffts and windowing refer to: f.j. harris, "on the use of windows for harmonic analysis with the discrete fourier transform", proc. ieee, vol. 66, no. 1, jan 1978, pp.51-83. this is available on request from crystal semiconductor. as illustrated in figure 17, the cs5101a typi- cally provides about 92 db s/(n+d) and 0.001% thd at 25 c. figure 18 illustrates only minor degradation in performance when the am- bient temperature is raised to 138 c. figure 19 and 20 illustrate that the cs5102a typically yields >92 db s/(n+d) and 0.001% thd even with a large change in ambient temperature. un- like conventional successive-approximation adcs, the signal-to-noise and dynamic range of the cs5101a and cs5102a are not limited by differential nonlinearities (dnl) caused by cali- bration errors. rather, the dominant noise source is broadband thermal noise which aliases into the baseband. this white broadband noise also ap- pears as an idle channel noise of 1/2 lsb (rms). sampling distortion like most discrete sample/hold amplifier designs, the inherent sample/hold of the cs5101a and cs5102a exhibits a frequency-dependent distor- tion due to nonideal sampling of the analog input voltage. the calibrated capacitor array used dur- ing conversions is also used to track and hold the analog input signal. the conversion is not per- formed on the analog input voltage per se, but is actually performed on the charge trapped on the capacitor array at the moment the hold com- mand is given. the charge on the array ideally assumes a linear relationship to the analog input voltage. any deviation from this linear relation- ship will result in conversion errors even if the conversion process proceeds flawlessly. at dc, the dac capacitor arrays voltage coeffi- cient dictates the converters linearity. this variation in capacitance with respect to applied signal voltage yields a nonlinear relationship be- tween the charge on the array and the analog input voltage and places a bow or wave in the transfer function. this is the dominant source of distortion at low input frequencies (fig- ures 17,18,19, and 20). the ideal relationship between the charge on the array and the input voltage can also be distorted cs5101a cs5102a 26 ds45f2
at high signal frequencies due to nonlinearities in the internal mos switches. dynamic signals cause ac current to flow through the switches connecting the capacitor array to the analog input pin in the track mode. nonlinear on-resistance in the switches causes a nonlinear voltage drop. this effect worsens with increased signal fre- quency and slew rate. this distortion is negligible at signal levels below -10 db of full-scale. noise an a/d converters noise can be described like that of any other analog component. however, the converters output is in digital form so any filtering of its noise must be performed in the digital domain. digitized samples of analog in- puts are often considered individual, static snap- shots in time with no uncertainty or noise. in reality, the result of each conversion depends on the analog input level and the instantaneous value of noise sources in the adc. if sequential sam- ples from the adc are treated as a "waveform", simple filtering can be implemented in software to improve noise performance with minimal proc- essing overhead. all analog circuitry in the cs5101a and cs5102a is wideband in order to achieve fast conversions and high throughput. wideband noise in the cs5101a and cs5102a integrates to 35 m v rms in unipolar mode (70 m v rms in bipo- lar mode). this is approximately 1/2 lsb rms with a 4.5v reference in both modes. figure 21 figure 18. cs5101a fft (ssc mode, 1-channel) dc 50 input frequency (khz) -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 signal level reletive to full scale (db) figure 17. cs5101a fft (ssc mode, 1-channel) dc 50 input frequency (khz) -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 signal level relative to full scale (db) dc 10 input frequency (khz) -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 signal level reletive to full scale (db) s/n+d: 92.01 db s/d: 101.8 db figure 19. cs5102a fft (ssc mode, 1-channel) dc 10 input frequency (khz) -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 signal level relative to full scale (db) figure 20. cs5102a fft (ssc mode, 1-channel) s/(n+d): 91.06 db s/d: 100.5 db t a = 138 c s/(n+d): 91.71 db s/d: 101.6 db s/(n+d): 92.01 db s/d: 101.8 db s/(n+d): 92.00db s/d: 101.6 db t a = 138 c cs5101a cs5102a ds45f2 27
shows a histogram plot of output code occur- rences obtained from 8192 samples taken from a cs5101a in the bipolar mode. hexadecimal code 7ffe was arbitrarily selected and the analog in- put was set close to code center. with a noiseless converter, code 7ffe would always appear. the histogram plot of the device has a "bell" shape with all codes other than 7ffe due to internal noise. figure 22 illustrates the noise histogram of the cs5102a. in a sampled data system all information about the analog input applied to the sample/hold ap- pears in the baseband from dc to one-half the sampling rate. this includes high-frequency com- ponents which alias into the baseband. low-pass (anti-alias) filters are therefore used to remove frequency components in the input signal which are above one-half the sample rate. however, all wideband noise introduced by the cs5101a and cs5102a still aliases into the baseband. this "white" noise is evenly spread from dc to one- half the sampling rate and integrates to 35 m v rms in unipolar mode. noise in the digital domain can be reduced by sampling at higher than the desired word rate and averaging multiple samples for each word. over- sampling spreads the devices noise over a wider band (for lower noise density), and averaging ap- plies a low-pass response which filters noise above the desired signal bandwidth. in general, the devices noise performance can be maximized in any application by always sampling at the maximum specified rate of 100 khz (cs5101a) or 20 khz (cs5102a) (for lowest noise density) and digitally filtering to the desired signal band- width. aperture jitter track-and-hold amplifiers commonly exhibit two types of aperture jitter. the first, more appropri- ately termed "aperture window", is an input voltage dependent variation in the aperture delay. its signal-dependency causes distortion at high frequencies. the proprietary architecture of the cs5101a and cs5102a avoids applying the in- put voltage across a sampling switch, thus avoiding any "aperture window" effects. the sec- ond type of aperture jitter, due to component noise, assumes a random nature. with only 100 ps peak-to-peak aperture jitter, the cs5101a and cs5102a can process full-scale signals up to 7ffc 7ffd 7ffe 8000 8001 7fff 7ffb 2048 4096 6144 8192 count noiseless cs5101a code (hexadecimal) counts: 0 0 989 6359 844 0 0 converter figure 21. 5101a histogram plot of 8192 conversion inputs 7ffe 7fff 8000(h) 8002 8003 8001 7ffd count noiseless cs5102a code (hexadecimal) counts: 05 1727 4988 1467 5 0 converter 8192 6144 4096 2048 figure 22. 5102a histogram plot of 8192 conversion inputs cs5101a cs5102a 28 ds45f2
1/2 the throughput frequency without significant errors due to aperture jitter. power supply rejection the power supply rejection performance of the cs5101a and cs5102a is enhanced by the on- chip self-calibration and an "auto-zero" process. drifts in power supply voltages at frequencies less than the calibration rate have negligible ef- fect on the devices accuracy. this is because the cs5101a and cs5102a adjust their offset to within a small fraction of an lsb during calibra- tion. above the calibration frequency the excellent power supply rejection of the internal amplifiers is augmented by an auto-zero process. any offsets are stored on the capacitor array and are effectively subtracted once conversion is initi- ated. figure 23 shows power supply rejection of the cs5101a and cs5102a in the bipolar mode with the analog input grounded and a 300 mv p- p ripple applied to each supply. power supply rejection improves by 6 db in the unipolar mode. cs5101a/cs5102a improvements over ear- lier cs5101/cs5102 the cs5101a/cs5102a are improved versions of the earlier cs5101/cs5102 devices. primary improvements are: 1) improved dnl at high temperature (>70 c) 2) improved input slew rate, yielding im- proved full scale settling between conversions. 3) modifying the previous ssh pin to ssh/sdl (simultaneous sample hold/se- rial data latch). the ssh/sdl new function provides a logic signal which frames the 16 data bits in ssc and frn serial modes. this signal is ideal for easy interface to serial to parallel shift registers (74hc595) and to dsp serial ports. table 3 summarizes all the improvements. power supply ripple frequency power supply rejection (db) 90 80 70 60 50 40 30 20 1 khz 10 khz 100 khz 1 mhz figure 23. power supply rejection cs5101a cs5102a ds45f2 29
function cs5101a/cs5102a cs5101/cs5102 better dnl no missing codes at +125 c some missed codes at +125 c faster fine charge cs5101a cs5102a cs5101 cs5102 slew rate (v/ m s) unipolar/fine 2 0.4 unipolar/fine 1.3 0.1 bipolar/fine 4 0.8 bipolar/fine 2.6 0.2 improved serial has serial data latch does not have serial data interface signal (ssh/sdl). latch (sdl) signal. clkin rate cs5101a maximum cs5101 maximum clkin is 9.216 mhz clkin is 8.0 mhz cs5102a maximum cs5102 maximum clkin is 2.0 mhz clkin is 1.6 mhz code and independent setting of 2s selecting unipolar input range bp/ up pin complement or offset binary forces offset binary operation, function coding (code) and bipolar or independent of the code pin state unipolar input range (bp/ up) crs/ fin pin can be high or low crs/ fin must be held during calibration low during calibration table 3. cs5101a/cs5102a improvements over cs5101/cs5102 schematic & layout review service confirm optimum schematic & layout before building your board. confirm optimum schematic & layout before building your board. for our free review service call applications engineering. for our free review service call applications engineering. call: (512) 445-7222 cs5101a cs5102a 30 ds45f2
pin descriptions negative digital power vd- sleep sleep (low power) mode reset & initiate calibration rst sckmod serial clock mode select master clock input clkin test test crystal output xout va+ positive analog power standby (calibrating) stby ain2 channel 2 analog input digital ground dgnd va- negative analog power positive digital power vd+ agnd analog ground tracking channel 1 trk1 refbuf reference buffer tracking channel 2 trk2 vref voltage reference coarse/fine charge control crs / fin ain1 channel 1 analog input simultaneous s/h / serial data latch ssh/sdl outmod output mode select hold & convert hold bp / up bipolar/unipolar select input channel select ch1 / 2code binary/2s complement select serial data clock sclk sdata serial data output 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 cs5102a cs5101a or vd- rst sleep clkin sckmod xout test stby va+ dgnd ain2 vd+ va- trk1 agnd trk2 refbuf crs/ fin vref ssh/sdl ain1 hold outmod ch1 /2 bp/ up sclk code sdata top view 22 20 24 19 21 23 25 327 2 426 28 1 12 14 16 18 13 15 17 8 6 10 5 7 9 11 cs5102a or cs5101a cs5101a cs5102a ds45f2 31
power supply connections vd+ - positive digital power, pin 7. positive digital power supply. nominally +5 volts. vd- - negative digital power, pin 1. negative digital power supply. nominally -5 volts. dgnd - digital ground, pin 6. digital ground [reference]. va+ - positive analog power, pin 25. positive analog power supply. nominally +5 volts. va- - negative analog power, pin 23. negative analog power supply. nominally -5 volts. agnd - analog ground, pin 22. analog ground reference. oscillator clkin - clock input, pin 3. all conversions and calibrations are timed from a master clock which can be externally supplied by driving clkin [this input ttl-compatible, cmos recommended]. xout - crystal output, pin 4. the master clock can be generated by tying a crystal across the clkin and xout pins. if an external clock is used, xout must be left floating. digital inputs hold - hold, pin 12. a falling transition on this pin sets the cs5101a or cs5102a to the hold state and initiates a conversion. this input must remain low for at least 1/tclk + 20 ns. when operating in free run mode, hold is disabled, and should be tied to dgnd or vd+. crs/ fin - coarse charge/fine charge control, pin 10. when brought high during acquisition time, crs/ fin forces the cs5101a or cs5102a into coarse charge state. this engages the internal buffer amplifier to track the analog input and charges the capacitor array much faster, thereby allowing the cs5101a or cs5102a to track high slewing signals. in order to get an accurate sample, the last coarse charge period before initiating a conversion (bringing hold low) must be longer than 0.75 m s (cs5101a) or 3.75 m s (cs5102a). similarly, the fine charge period immediately prior to conversion must be at least 1.125 m s (cs5101a) or 5.625 m s (cs5102a). the crs/ fin pin must be low during conversion time. for normal operation, crs/ fin should be tied low, in which case the cs5101a or cs5102a will automatically enter coarse charge for 6 clock cycles immediately after the end of conversion. cs5101a cs5102a 32 ds45f2
ch1/ 2 - left/right input channel select, pin 13. status at the end of a conversion cycle determines which analog input channel will be acquired for the next conversion cycle. when in free run mode, ch1/ 2 is an output, and will indicate which channel is being sampled during the current acquisition phase. sleep - sleep, pin 28. when brought low causes the cs5101a or cs5102a to enter a power-down state. all calibration coefficients are retained in memory, so no recalibration is needed after returning to the normal operating mode. if using the internal crystal oscillator, time must be allowed after sleep returns high for the crystal oscillator to stabilize. sleep should be tied high for normal operation. code - 2s complement/binary coding select, pin 16. determines whether output data appears in 2s complement or binary format. if high, 2s complement; if low, binary. bp/ up - bipolar/unipolar input range select, pin 17. when low, the cs5101a or cs5102a accepts a unipolar input range from agnd to vref. when high, the cs5101a or cs5102a accepts bipolar inputs from -vref to +vref. sckmod - serial clock mode select, pin 27. when high, the sclk pin is an input; when low, it is an output. used in conjunction with outmod to select one of 4 output modes described in table 2. outmod - output mode select, pin 18. the status of sckmod and outmod determine which of four output modes is utilized. the four modes are described in table 2. sclk - serial clock, pin 14. serial data changes status on a falling edge of this input, and is valid on a rising edge. when sckmod is high sclk acts as an input. when sckmod is low the cs5101a or cs5102a generates its own serial clock at one-fourth the master clock frequency and sclk is an output. rst - reset, pin 2. when taken low, all internal digital logic is reset. upon returning high, a full calibration sequence is initiated which takes 11,528,160 clkin cycles (cs5101a) or 2,882,040 clkin cycles (cs5102a) to complete. during calibration, the hold input will be ignored. the cs5101a or cs5102a must be reset at power-up for calibration, however; calibration is maintained during sleep mode, and need not be repeated when resuming normal operation. analog inputs ain1, ain2 - channel 1 and 2 analog inputs, pins 19 and 24. analog input connections for the left and right input channels. vref - voltage reference, pin 20. the analog reference voltage which sets the analog input range. in unipolar mode vref sets full-scale; in bipolar mode its magnitude sets both positive and negative full-scale. cs5101a cs5102a ds45f2 33
digital outputs stby - standby (calibrating), pin 5. indicates calibration status after reset. remains low throughout the calibration sequence and returns high upon completion. sdata - serial output, pin 15. presents each output data bit on a falling edge of sclk. data is valid to be latched on the rising edge of sclk. ssh/sdl - simultaneous sample/hold / serial data latch, pin 11. used to control an external sample/hold amplifier to achieve simultaneous sampling between channels. in frn and ssc modes (sclk is an output), this signal provides a convenient latch signal which forms the 16 data bits. this can be used to control external serial to parallel latches, or to control the serial port in a dsp. trk1, trk2 - tracking channel 1, tracking channel 2, pins 8 and 9. falls low at the end of a conversion cycle, indicating the acquisition phase for the corresponding channel. the trk1 or trk2 pin will return high at the beginning of conversion for that channel. analog outputs refbuf - reference buffer output, pin 21. reference buffer output. a 0.1 m f ceramic capacitor must be tied between this pin and va-. miscellaneous test - test, pin 26. allows access to the cs5101as and the cs5102as test functions which are reserved for factory use. must be tied to vd+. cs5101a cs5102a 34 ds45f2
parameter definitions linearity error the deviation of a code from a straight line passing through the endpoints of the transfer function after zero- and full-scale errors have been accounted for. "zero-scale" is a point 1/2 lsb below the first code transition and "full-scale" is a point 1/2 lsb beyond the code transition to all ones. the deviation is measured from the middle of each particular code. units in % full-scale. differential linearity minimum resolution for which no missing codes is guaranteed. units in bits. full scale error the deviation of the last code transition from the ideal (vref-3/2 lsbs). units in lsbs. unipolar offset the deviation of the first code transition from the ideal (1/2 lsb above agnd) when in unipolar mode (bp/up low). units in lsbs. bipolar offset the deviation of the mid-scale transition (011...111 to 100...000) from the ideal (1/2 lsb below agnd) when in bipolar mode (bp/ up high). units in lsbs. bipolar negative full-scale error the deviation of the first code transition from the ideal when in bipolar mode (bp/ up high). the ideal is defined as lying on a straight line which passes through the final and mid-scale code transitions. units in lsbs. signal to peak harmonic or noise the ratio of the rms value of the signal to the rms value of the next largest spectral component below the nyquist rate (excepting dc). this component is often an aliased harmonic when the signal frequency is a significant proportion of the sampling rate. expressed in decibels. total harmonic distortion the ratio of the rms sum of all harmonics to the rms value of the signal. units in percent. signal-to-(noise + distortion) the ratio of the rms value of the signal to the rms sum of all other spectral components below the nyquist rate (excepting dc), including distortion components. expressed in decibels. aperture time the time required after the hold command for the sampling switch to open fully. effectively a sampling delay which can be nulled by advancing the sampling signal. units in nanoseconds. aperture jitter the range of variation in the aperture time. effectively the "sampling window" which ultimately dic- tates the maximum input signal slew rate acceptable for a given accuracy. units in picoseconds. cs5101a cs5102a ds45f2 35
cs5101a ordering guide model conversion time throughput linearity temperature package cs5101a-jp8 8.13 m s 100 khz 0.003% 0 to 70 c 28-pin plastic dip cs5101a-kp8 8.13 m s 100 khz 0.002% 0 to 70 c 28-pin plastic dip cs5101a-jp16 16.25 m s 50 khz 0.003% 0 to 70 c 28-pin plastic dip cs5101a-jl8 8.13 m s 100 khz 0.003% 0 to 70 c 28-pin plcc cs5101a-kl8 8.13 m s 100 khz 0.002% 0 to 70 c 28-pin plcc cs5101a-jl16 16.25 m s 50 khz 0.003% 0 to 70 c 28-pin plcc cs5101a-ap8 8.13 m s 100 khz 0.003% -40 to 85 c 28-pin plastic dip cs5101a-bp8 8.13 m s 100 khz 0.002% -40 to 85 c 28-pin plastic dip cs5101a-al8 8.13 m s 100 khz 0.003% -40 to 85 c 28-pin plcc cs5101a-bl8 8.13 m s 100 khz 0.002% -40 to 85 c 28-pin plcc cs5101a-sd8 8.13 m s 100 khz 0.004% -55 to 125 c 28-pin cerdip cs5101a-td8 8.13 m s 100 khz 0.003% -55 to 125 c 28-pin cerdip cs5101a-se8 8.13 m s 100 khz 0.004% -55 to 125 c 28-pin lcc cs5101a-te8 8.13 m s 100 khz 0.003% -55 to 125 c 28-pin lcc 5962-9169101mxa 8.13 m s 100 khz 0.004% -55 to 125 c 28-pin cerdip 5962-9169102mxa 8.13 m s 100 khz 0.003% -55 to 125 c 28-pin cerdip 5962-9169101m3a 8.13 m s 100 khz 0.004% -55 to 125 c 28-pin lcc 5962-9169102m3a 8.13 m s 100 khz 0.003% -55 to 125 c 28-pin lcc discontinued equivalent part number recommended device cs5101a-sd8b 5962-9169101mxa cs5101a-td8b 5962-9169102mxa cs5101a-se8b 5962-9169101m3a cs5101a-te8b 5962-9169102m3a cs5102a ordering guide model conversion time throughput linearity temperature package cs5102a-jp 40 m s 20 khz 0.003% 0 to 70 c 28-pin plastic dip cs5102a-kp 40 m s 20 khz 0.0015% 0 to 70 c 28-pin plastic dip cs5102a-jl 40 m s 20 khz 0.003% 0 to 70 c 28-pin plcc cs5102a-kl 40 m s 20 khz 0.0015% 0 to 70 c 28-pin plcc cs5102a-ap 40 m s 20 khz 0.003% -40 to 85 c 28-pin plastic dip cs5102a-bp 40 m s 20 khz 0.0015% -40 to 85 c 28-pin plastic dip cs5102a-al 40 m s 20 khz 0.003% -40 to 85 c 28-pin plcc cs5102a-bl 40 m s 20 khz 0.0015% -40 to 85 c 28-pin plcc cs5102a-sd 40 m s 20 khz 0.004% -55 to 125 c 28-pin cerdip cs5102a-td 40 m s 20 khz 0.002% -55 to 125 c 28-pin cerdip cs5102a-se 40 m s 20 khz 0.004% -55 to 125 c 28-pin lcc cs5102a-te 40 m s 20 khz 0.002% -55 to 125 c 28-pin lcc 5962-9169201mxa 40 m s 20 khz 0.004% -55 to 125 c 28-pin cerdip 5962-9169202mxa 40 m s 20 khz 0.002% -55 to 125 c 28-pin cerdip 5962-9169201m3a 40 m s 20 khz 0.004% -55 to 125 c 28-pin lcc 5962-9169202m3a 40 m s 20 khz 0.002% -55 to 125 c 28-pin lcc discontinued equivalent part number recommended device cs5102a-sdb 5962-9169201mxa cs5102a-tdb 5962-9169202mxa cs5102a-seb 5962-9169201m3a cs5102a-teb 5962-9169202m3a cs5101a cs5102a 36 ds45f2
37 copyright ? cirrus logic, inc. 1998 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cdb5101a cdb5102a evaluation board for cs5101a and cs5102a features l serial to parallel conversion l adjustable voltage reference l 5 v regulators l digital and analog patch areas description the cdb5101a/5102a evaluation board allows fast evaluation of the cs5101a and cs5102a 2-channel, 16-bit analog-to-digital converters. analog inputs are via bnc connectors. digital outputs are available both directly from the adc in serial form, and in 16 bit parallel form. an adjustable monolithic voltage reference is included. ordering information cdb5101a evaluation board cdb5102a evaluation board i -15v +15v va+ va- vd+ vd- vref refbuf ain1 ain2 code bp/up sckmod outmod sleep voltage reference serial to parallel conversion clkin xout hold sdata sclk ssh/sdl digital patch area header ext va- ain1 ain2 5v regulators 0v agnd vl+ +5v 0v dgnd mode select switches ch1/ch2 hold header cs5101a or cs5102a input buffers serial output buffers analog patch area clkin mar 95 ds45db3
power supplies figure 1 shows the power supply arrangements. the analog section of the board is powered by 12/15 volts, which is regulated down to 5v for the adc. a separate +5v digital supply is required to power the discrete logic. analog input the cs5101a/02a converters have a two-chan- nel multiplexer input. separate amplifiers (see figure 2) are provided on the evaluation board to drive each input independently. if the con- verter is used in frn mode, the multiplexer "ping-pongs" between channels. if only one sig- nal is to be digitized in frn mode at full speed, the ain1 and ain2 pins on the converter should be shorted together. then the amplifier circuitry for the unused channel should be disconnected. for example, if only analog input one is used (in frn mode) as the input, short the ain1 and ain2 pins of the converter and remove r15 and c15. if you do not want to use the on-board amplifi- ers, connect your signal to tp27 for channel 1 and tp32 for channel 2. use tp28 and tp31 to break the connection to the output of the on- board buffers. your own buffer amplifiers may be installed in the 2 analog patch areas. for criti- cal 2 channel applications, keep the signal path for the 2 channels identical. voltage reference figure 3 shows the lti019-4.5 voltage refer- ence, which is buffered and filtered to reduce output impedance and noise. +15v -15v c20 c19 c21 c18 0.22 m f 0.47 m f +5va - 5va j1 + c23 10 m f c22 + 10 m f 0.22 m f d2 d1 0.47 m f c25 + c24 10 m f 0.1 m f d3 +12/15v -12/15v agnd dgnd +5v logic tp gnd +5vl tp - va+ tp - va - tp +5v 78l05 out com u7 in 79l05 out com in u8 figure 1. power supplies cdb5101a/5102a 38 ds45db3
1 5 tp28 tp29 tp27 tp31 tp30 tp32 2.0k r27 1.0k 2.0k 1.0k tp34 tp33 -15v -15v 2.0k 62pf 1 m f .1 m f 1 2 3 4 5 6 7 1 m f 1.0k 1 m f + + .1 m f 2 3 4 6 7 .1 m f 1 m f 2.0k 62pf 1nf 50 50 1nf npo npo ain1 ain2 + u9 opa627 opa627 u10 + 1.0k +15v +15v c34 r17 c31 c30 r19 r14 c16 c15 r15 c32 c33 c38 c37 .1 m f r22 c35 c36 r20 c39 r21 r28 r18 analog input 1 analog input 2 c45 0.01 m f c48 0.01 m f * * * amplifiers u9 and u10 have gain of +1, as resistors r18 and r21 are left off the board. input unipolar 0v to +4.5v bipolar -4.5v to +4.5v fig. 4 fig. 4 figure 2. input buffer circuit. c2 0.1 m f + c3 10 m f tp77 r2 25 k out trim gnd in +15v 2 4 5 6 cw 2 k c1 15 m f r1 op27 0.1 m f 0.01 m f 2 3 4 7 6 22 47 k 1 k +15v -15v 0.1 m f 10 m f + 0.1 m f 1 k + c44 r25 c43 c42 r23 u11 c40 r26 r24 c41 lt1019-4.5 u6 vref fig. 4 figure 3. voltage reference cdb5101a/5102a ds45db3 39
master clock figure 4 shows the local connections to the cs5101a or cs5102a. the appropriate crystal components are installed at the factory, which utilize the on-chip oscillator. for use with an ex- ternal clock, cut jumper j00 and drive a cmos level compatible clock into the clkin bnc connector. r30 is an optional 50 w terminating resistor if a pulse generator is used. sampling clock ( hold ) generation the evaluation board is shipped in frn mode, which requires no externally generated hold signal. alternate modes may be selected using dip switch 3 and 4 (see table 2). an external hold may be connected using the hold bnc connector. va+ tst clkin xout 10 r4 c7 c6 + 1 m f 0.1 m f 23 1 10 r11 + c13 c14 c12 c11 + -5va 1 m f 0.1 m f 1 m f 0.1 m f va- vd- vref agnd 20 see 25 26 vd+ 7 u1 cs5101a or cs5102a vd+ va - +5va + c4 c5 1 m f 0.1 m f 3 y1 j00 c9 tp00 4 c8 tp00 r5 clkin 10m 19 24 ain1 ain2 tp25 22 12 hold hold r13 10k r12 10k 10 crs/fin fig. 3 refbuf 21 va- 0.1 m f tp00 s1 reset 0.1 m f c10 10k r6 vd+ 2 6 dgnd rst code bp/up sckmod outmod sleep ch1/ch2 sdata sclk ssh/sdl stby trk1 trk2 16 17 27 18 28 13 15 14 11 5 8 9 vd+ 1 2 3 4 5 6 s2 r7 10k code bp/up outmod sleep ch1/ch2 sdata fig. 5, 6 sclk fig. 5, 6 ssh/sdl fig. 5, 6 7 6 5 4 3 2 r22 68 c17 trk1 fig. 6 trk2 fig. 6 ch1/ch2 fig. 5 r9 47k r31 68 r30 50 see fig. 2 see fig. 2 sckmod figure 4. adc connections 8.192 mhz 1.6 mhz y1 10 pf 30 pf c8 10 pf 30 pf c9 cdb5101a cdb5102a oscillator component values cdb5101a/5102a 40 ds45db3
control signals figure 5 shows 2 headers are provided for serial data output and control signals. jp3 provides sdata and ssh/sdl outputs. it also allows ac- cess to sclk & ch1/ ch2 which may be inputs or outputs depending on the serial mode selected by the dip switches. jumpers j10, j11, j12, & j13 must be set to correspond with the appropri- ate directions of sclk and ch1/ ch2. jp5 provides output only access to the +5v logic supply, sclk, sdata and slatch, the serial to parallel latching control. serial to parallel conversion when operating in the frn or ssc serial port modes, the cs5101a/02a readily provides the three signals (sclk, sdata, and ssh/sdl) to support serial to parallel conversion of its output data. figure 6 shows 2 74hc595?s provided to con- vert the serial output of the adc to parallel. a handshake flip-flop, u3, is provided for the par- allel interface if required. when parallel data is available to read, drdy goes low. the com- puter reads the data and sets dack high and then low. this resets the flip-flop for the next word. jp4 selects whether both ch1 and ch2 data appears alternately, or ch1 only, or ch2 only. sclk direction j10 in out jp3 j11 j12 oe1 oe2 y0 y1 y2 y3 y4 y5 74hc365 3 5 7 9 11 13 2 4 6 10 12 14 1 15 u12 .1 m f c48 +5v out in a0 a1 a2 a3 a4 a5 r32 68 hdr5d hdr10d +5v jp5 10 r3 + c47 10 m f r33 68 ssh/sdl sdata sclk slatch ch1/ch2 j13 direction ch1/ch2 sdata sclk ssh/sdl ch1/ch2 +5v +5v slatch sclk sdata fig. 4 fig. 4 fig. 4 fig. 4 fig. 6 figure 5. serial output buffers cdb5101a/5102a ds45db3 41
13 11 12 9 12 11 8 14 14 shift clk latch clk data in oe q h g q f q e q d q c q b q a q u4 74hc595 d15 (msb) d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (lsb) dack cs drdy shift clk latch clk data out q h g q f q e q d q c q b q a q data in u5 74hc595 7 6 5 4 3 2 1 15 7 6 5 4 3 2 1 15 40 way header y x tp00 oe gnd 10 16 rst +5vl 0.1 m f c27 10 16 rst +5vl 0.1 m f c29 jp2 8 gnd u3 q d cl q u2 12 13 +5vl tp00 7 1 6 5 tp00 3 2 4 14 +5vl 11 sdata sclk tp00 u2 9 10 8 6 4 5 u2 clk 74hc74 8 9 10 11 12 13 +5v u3 1 2 3 4 5 6 +5v r16 10k jp4 hdr8d r6 10k r10 10k trk1 trk2 ssh/sdl slatch both ch2 ch1 q d s r fig. 5 fig. 4 fig. 4 fig. 4 fig. 4 fig. 4 figure 6. serial to parallel converter cdb5101a/5102a 42 ds45db3
dip switches tables 1 and 2 show the dip switch settings. miscellaneous hints on using the evaluation board always depress the reset button after powering up the board. the cs5101a & cs5102a are self calibrating adc?s which require a reset to initi- ate the internal calibration procedure. crystal semiconductor has software, available on request, which allows the evaluation board to be connected to a metrabyte pio12 parallel i/o card (which uses an intel 8255 pio chip), which is plugged into an ibm pc or compatible com- puter. the software is assembly language drivers to read the data from the board. also included is source code, in fortran, of an fft routine. table 2. output mode selections open 1 2 4 5 6 3 code bp/up sckmod sleep outmod ch1/ch2* 2's complement bipolar selects serial port mode. see table 2. normal mode ain1 binary unipolar sleep mode ain2 open close *sw6 is not active when the converter is operating in the frn mode. table 1. dip switch selections sckmod (sw4) outmod (sw3) cs5101a/cs5102a output mode close close (frn) free run close open (ssc) synchronous self clocking open close (rbt) registered burst transmission open open (pdt) pipelined data transmission note: closed = low = 0; open = high = 1. cdb5101a/5102a ds45db3 43
figure 7. cdb5101a/02a rev. b layout cdb5101a/5102a 44 ds45db3
figure 8. cdb5101a/02a rev. b component side cdb5101a/5102a ds45db3 45
figure 9. cdb5101a/02a rev. b solder side cdb5101a/5102a 46 ds45db3
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